`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:55:20 09/03/2012
// Design Name:   main
// Module Name:   C:/Users/Maria Victoria/Desktop/lab2/TestDeFuncionalidad.v
// Project Name:  lab2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: main
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TestDeFuncionalidad;

	// Inputs
	reg rst_i;
	reg sensor_sync_i;
	reg walk_i;
	reg reprogram_i;
	reg [1:0] Time_Parameter_Selector_i;
	reg [3:0] Time_Value_i;
	reg clk_i;

	// Outputs
	wire [7:0] LEDs_o;
	wire cloo;
	wire [3:0] display_o;

	// Instantiate the Unit Under Test (UUT)
	main uut (
		.rst_i(rst_i), 
		.sensor_sync_i(sensor_sync_i), 
		.walk_i(walk_i), 
		.reprogram_i(reprogram_i), 
		.Time_Parameter_Selector_i(Time_Parameter_Selector_i), 
		.Time_Value_i(Time_Value_i), 
		.clk_i(clk_i), 
		.LEDs_o(LEDs_o),
		.cloo(cloo),
		.display_o(display_o)
	);

	initial begin
		// Initialize Inputs
		rst_i = 0;
		sensor_sync_i = 0;
		walk_i = 0;
		reprogram_i = 0;
		Time_Parameter_Selector_i = 10;
		Time_Value_i = 7;
		clk_i = 0;

		// Wait 100 ns for global reset to finish
		#20000;
		walk_i = 1;
		#100;
		walk_i = 0;
		
		
	

		
		
        
		// Add stimulus here

	end
   always #20 clk_i <= ~clk_i;       
endmodule

